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May 1997
ML6698* 100BASE-TX Physical Layer with 5-Bit Interface
GENERAL DESCRIPTION
The ML6698 is a high-speed physical layer transceiver that provides a 5-bit (or symbol) interface to unshielded twisted pair cable media. The ML6698 is well suited for adapter card applications using the DEC 21143, the Macronix MX98713, or equivalent Media Access Controllers (MACs). The ML6698 may be used in other 100BASE-TX applications requiring the 5-bit interface as well as FDDI-over-copper applications. The ML6698 integrates 125MHz clock recovery/ generation, receive adaptive equalization, baseline wander correction and MLT-3/10BASE-T transmitter.
FEATURES
s s s s s s s s
5-bit (or symbol) parallel interface Compliant to IEEE 802.3u 100BASE-TX standard Compliant to ANSI X3T12 TP-PMD (FDDI) standard Single-jack 10BASE-T/100BASE-TX solution when used with external 10Mbps PHY 125MHz receive clock recovery/generation Baseline wander correction Adaptive equalization and MLT-3 encoding/decoding Supports full-duplex operation
*Some Packages Are End Of Life As Of August 1, 2000
BLOCK DIAGRAM (PLCC Pin Configuration)
41
40
10BTTXINP
44
TXC
CLOCK SYTHESIZER
10BTTXINN
TPOUTP
2 3 4 5 6
TSM4 TSM3 TSM2 TSM1 TSM0 CLOCK AND DATA RECOVERY TPINP EQUALIZER BLW CORRECTION MLT-3 DECODER LOOPBACK MUX DESERIALIZER RSM2 RSM1 RSM0 CONTROL LOGIC CMREF RGMSET SDO TPINN SERIALIZER NRZ TO NRZI AND NRZI TO MLT-3 ENCODER 100BASE-TX/10BASE-T TWISTED PAIR DRIVER TPOUTN RTSET
34 33 31
38 37 39 30 24
16 8 9 11 13 15
RXC RSM4 RSM3
NRZI TO NRZ DECODER
SEL100/10
25
42
PWRDN
7
LPBK
1
ML6698
PIN CONFIGURATION
ML6698 44-Pin PLCC (Q44)
10BTTXINN
40 39 38 37 36 35 34 33 32 31 30 29 19 20 21 22 23 24 25 26 27 28
6
5
4
3
2
1
44
43
42
PWRDN RSM4 RSM3 DGND1 RSM2 DVCC1 RSM1 DGND2 RSM0 RXC DGND3
7 8 9 10 11 12 13 14 15 16 17 18
10BTTXINP
41
AGND1
AVCC1
TSM0
TSM1
TSM2
TSM3
TSM4
LPBK
TXC
CMREF TPINP TPINN AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET NC
DVCC5
DVCC2
DGND5
SDO
DGND4A
DGND4B
DGND4C
ML6698 44-Pin TQFP (H44-10)
10BTTXINN
34 33 32 31 30 29 28 27 26 25 24 23 13 14 15 16 17 18 19 20 21 22
SEL100/10
44
43
42
41
40
39
38
37
36
35
PWRDN RSM4 RSM3 DGND1 RSM2 DVCC1 RSM1 DGND2 RSM0 RXC DGND3
1 2 3 4 5 6 7 8 9 10 11 12
10BTTXINP
AGND1
AVCC1
TSM0
TSM1
TSM2
TSM3
TSM4
LPBK
TXC
AVCC3
NC
NC
CMREF TPINP TPINN AVCC2 AGND2 TPOUTP TPOUTN AGND3 RTSET RGMSET NC
SEL100/10
DVCC2
DGND4A
DGND4B
DGND4C
DVCC5
DGND5
2
AVCC3
SDO
NC
NC
ML6698
PIN DESCRIPTION (Pin numbers for TQFP package in parentheses)
PIN NAME DESCRIPTION
1 2-6 7
(39) (40-44) (1)
AGND1 TSM<4:0> PWRDN RSM<4:0>
Analog ground. Transmit data TTL inputs. TSM<4:0> inputs accept TX data symbols. Data appearing at TSM<4:0> are clocked into the ML6698 on the rising edge of TXC. Device power down input. A low signal powers down all ciruits of the ML6698, and dissipates less than 20mA. Receive data TTL outputs. RSM<4:0> outputs may be sampled synchronously with RXC's rising edge.
8,9, (2, 3, 11,13, 5, 7, 9) 15 10 12 14 16 (4) (6) (8) (10)
DGND1 DVCC1 DGND2 RXC
Digital ground. Digital +5V power supply. Digital ground. Recovered receive symbol clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at TPINP/N when data is present. Receive data at RSM<4:0> change on the falling edges and should be sampled on the rising edges of this clock. RXC is phase aligned to TXC when 100BASE-TX signal is not present at TPINP/N Digital ground. Digital +5V power supply. Digital ground. Digital ground. Digital ground. Digital +5V power supply. Digital ground. Signal detect TTL output. A high output level indicates 100BASE-TX activity at TPINP/N with an amplitude exceeding the preset threshold. The signal detect function is always active independent of the configuration of the SEL100/10 pin. Speed select TTL input. Driving this pin low disables 100BASE-TX transmit and receive functions, and enables the 10BASE-T transmit path from 10BTTXINP/N to TPOUTP/N. A high signal on SEL100/10 disables the 10BTTXINP/N inputs and enables 100BASE-TX operation. Analog positive power supply. Equalizer bias resistor input. An external 9.53ky, 1% resistor connected between RGMSET and AGND3 sets internal time constants controlling the receive equalizer transfer function. Transmit level bias resistor input. An external 2.49ky, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current for the twisted pair transmit level. Analog ground. Transmit twisted pair outputs. This differential current output pair drives MLT-3 waveforms into the network coupling transformer in 100BASE-TX mode, and 10BASE-T or FLP waveforms in 10BASE-T mode. Analog ground. Analog +5V power supply. Receive twisted pair inputs. This differential input pair receives 100BASE-TX signals from the network.
17 18 19 20 21 22 23 24
(11) (12) (13) (14) (15) (16) (17) (18)
DGND3 DVCC2 DGND4A DGND4B DGND4C DVCC5 DGND5 SD0
25
(19)
SEL100/10
28 30
(22) (24)
AVCC3 RGMSET
31
(25)
RTSET
32
(26)
AGND3 TPOUTN/P
33,34 (27,28)
35 36
(29) (30)
AGND2 AVCC2 TPINN/P
37,38 (31, 32)
3
ML6698
PIN DESCRIPTION
PIN
(Continued)
DESCRIPTION
NAME
39
(33)
CMREF
Receiver common-mode reference output. This pin provides a common-mode bias point for the twisted-pair media line receiver. A typical value for CMREF is (VCC-1.26)V.
40,41 (34,35)
10BTTXINN/P 10BASE-T transmit waveform inputs. The ML6698 presents a linear copy of the input at 10BTTXINN/P to the TPOUTN/P outputs when the ML6698 functions in 10BASE-T mode. Signals presented to these pins must be centered at VCC/2 with a single ended amplitude of 0.25V. LPBK Loopback TTL input pin. Tying this pin to ground places the part in loopback mode; data at RSM<4:0> are serialized, MLT-3 encoded, equalized then sent to the receive PLL for clock recovery and sent to the RSM<4:0> outputs. Floating this pin or tying it to VCC places the part in its normal mode of operation. Analog +5V power supply. Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal transmit PLL clock multiplier. This pin should be driven by an external 25MHz clock at TTL or CMOS levels.
42
(36)
43 44
(37) (38)
AVCC1 TXC
4
ML6698
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. VCC Supply Voltage Range ................... GND -0.3V to 6V Input Voltage Range Digital Inputs ....................... GND -0.3V to VCC + 0.3V TPINP, TPINN, 10BTTXINP, 10BTTXINN ..................... GND -0.3V to VCC + 0.3V Output Current TPOUTP, TPOUTN .............................................. 60mA All other outputs .................................................. 10mA Junction Temperature ............................................. 150C Storage Temperature .............................. .. -65C to 150C Lead Temperature (Soldering, 10 sec) ..................... 260C
OPERATING CONDITIONS
VCC Supply Voltage ............................................ 5V 5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. TA, Ambient temperature ................................ 0C to 70C RGMSET ..................................................... 9.53ky 1% RTSET .......................................................... 2.49ky 1% Receive transformer insertion loss ........................ <-0.5dB
DC ELECTRICAL CHARACTERISTICS
Over full range of operating conditions unless otherwise specified (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TTL Inputs (TSM<4:0>, TXC, SEL100/10, PWRDN, LPBK) VIL VIH IIL IIH Input Low Voltage Input High Voltage Input Low Current Input High Current IIL = -400A IIH = 100A VIN = 0.4V VIN = 2.7V 2.0 -200 100 0.8 V V A A
TTL Outputs (RSM<4:0>, RXC, SDO) VOL VOH Receiver VICM VID RIDR IICM IRGM IRT Transmitter ITD100 ITD10 ITOFF ITXI TPOUTP/N 100BASE-TX Mode Differential Output Current TPOUTP/N 10BASE-T Mode Differential Output Current TPOUTP/N Off-State Output TPOUTP/N Differential Output Current Imbalance RL = 200, 1% RL = 200, 1% Note 2, 3 19 55 0 60 21 65 1.5 500 mA mA mA A TPINP/N Input Common-Mode Voltage TPINP-TPINN Differential Input Voltage Range TPINP-TPINN Differential Input Resistance TPINP/N Common-Mode Input Current RGMSET Input Current RTSET Input Current RGMSET = 9.53ky RTSET = 2.49ky 130 500 100y Termination across TPINP/N -3.0 10.0k +10 VCC - 1.26 3.0 V V y A A A Output Low Voltage Output High Voltage IOL = 4mA IOH = -4mA 2.4 0.4 V V
5
ML6698
DC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Transmitter (Continued) XERR XCMP100 VOCM10 VICM10 TPOUTP/N Differential Output Current Error TPOUTP/N 100BASE-X Output Current Compliance Error TPOUTP/N 10BASE-T Output Voltage Compliance Range 10BTTXNN/P Input Common-Mode Voltage Range VOUT = VCC; Note 3 VOUT = VCC 2.2V; referred to IOUT at VCC ITD10 remains within specified values -5.0 +5.0 %
(Continued)
CONDITIONS MIN TYP MAX UNITS
-2.0 VCC - 2.7 VCC/2 - 0.3
+2.0 VCC + 2.7 VCC/2 + 0.3
% V V
Power Supply Current ICC100 ICC10 ICCOFF Supply Current, 100BASE-TX Operation, Transmitting Supply Current, 10BASE-T Mode Supply Current Power Down Mode PWRDN Current into all VCC pins, VCC = 5.25V (Note 2) 195 155 260 175 20 mA mA mA
AC ELECTRICAL CHARACTERISTICS
Over full range of operating conditions unless otherwise specified
SYMBOL tTR/F tTM tTDC tTJT XOST tTXP tRXDC PARAMETER TPOUTP-TPOUTN Differential Rise/Fall Time TPOUTP-TPOUTN Differential Rise/Fall Time Mismatch TPOUTP-TPOUTN Differential Output Duty Cycle Distortion TPOUTP-TPOUTN Differential Output Peak-to-Peak Jitter TPOUTP-TPOUTN Differential Output Voltage Overshoot Transmit Bit Delay Receive Bit Delay CONDITIONS Notes 5, 6; for any legal code sequence Notes 5, 6; for any legal code sequence Notes 4, 6 Note 6 Notes 6, 7 Note 8 Note 9 MIN 3.0 -0.5 -0.5 300 TYP MAX 5.0 0.5 0.5 1400 5 10.5 15.5 UNITS ns ns ns ps % Bit Times Bit Times
6
ML6698
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER MII (Media-Independent Interface) XBTOL tTPWH tTPWL tRPWH tRPWL tTPS tTPH TX Output Clock Frequency Tolerance TXC pulse width HIGH TXC pulse width LOW RXC pulse width HIGH RXC pulse width LOW Setup time, TSM<4:0> Data Valid to TXC Rising Edge (1.4V point) Hold Time, TSM<4:0> Data Valid After TXC Rising Edge (1.4V point) Time that RSM<4:0> Data are Valid Before RXC Rising Edge (1.4V point) Time that RSM<4:0> Data are Valid After RXC Rising Edge (1.4V point) RXC 10% - 90% Rise Time RXC 90%-10% Fall Time 25MHz frequency -100 14 14 14 14 12 3 +100 ppm ns ns ns ns ns ns
(Continued)
CONDITIONS MIN TYP MAX UNITS
tRCS
10
ns
tRCH
10
ns
tRPCR tRPCF
Note 1. Note 2.
6 6
ns ns
Note 3. Note 4. Note 5.
Note 6. Note 7.
Note 8. Note 9.
Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Measured using the test circuit shown in Fig. 1, under the following conditions: RLP = 200y, RLS = 49.9y, RTSET = 2.49ky. All resistors are 1% tolerance. Output current amplitude is IOUT = 40 3 1.25V/RTSET. Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence. Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the external network coupling transformer and EMI/RFI emissions filter. Differential test load is shown in fig. 1 (see note 3). Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge. Symbol /J/ at TSM <4:0> sampled by TXC to first bit of /J/ at MDI. First bit of /J/ at MDI to first rising edge of RXC after the last part of the /J/ appears at RSM <4:0>.
VCC TPOUTP RLP 200 2:1 1
RLP 200 TPOUTN RLS 49.9
2 RLS 49.9
Figure 1. Test Circuit
7
ML6698
tTPWL
tTPWH TXC
TSM<4:0>
tTPS
tTPH
Figure 2.
tTPWH RXC
tTPWL
tRPCF
tRPCR
RSM<4:0>
tRCS
tRCM
Figure 3.
8
ML6698
FUNCTIONAL DESCRIPTION
TRANSMIT SECTION 100BASE-TX Operation The transmitter accepts scrambled 5-bit symbols clocked in at 25MHz and outputs MLT-3 signals onto the twisted-pair media at 100Mbps. The on-chip transmit PLL converts a 25MHz TTL-level clock at TXC to an internal 125MHz bit clock. TXC from the ML6698 clocks scrambled transmit symbols from the MAC into the ML6698's TSM<4:0> input pins. Symbols from the TSM<4:0> inputs are converted from parallel to serial form at the 125MHz clock rate. The serial transmit data is converted to MLT-3 3-level code and driven differentialy out of the TPOUTP and TPOUTN pins at nominal 2V levels with the proper loads. The transmitter is designed to drive a center-tapped transformer with a 2:1 winding ratio, so a differential 400 ohm load is used on the transformer primary to properly terminate the 100 ohm cable and termination on the secondary. The transformer's center tap must be tied to VCC. A 2:1 transformer allows using a 20mA output current in 100BASE-TX mode. Using a 1:1 transformer would have required twice the output current and increased the on-chip power dissipation. An external 2.49kW, 1% resistor at the RTSET pin creates the correct output levels at TPOUP/N. 10BASE-T In 10BASE-T mode, the transmitter acts as a linear buffer with a gain of 10. 10BASE-T inputs (Manchester data and normal link pulses) at 10BTTXINP/N appear as full-swing signals at TPOUTP/N in this mode. Inputs to the 10BTTXINP/N pins should have a nominal 0.25V differential amplitude and a common-mode voltage of VCC/2, and should also be waveshaped or filtered to meet the 10BASE-T harmonic content requirements. The ML6698 does not provide any 10BASE-T transmit filtering. RECEIVE SECTION The receiver converts 3-level MLT-3 signals from the twisted-pair media to 5-bit scrambled symbols at RSM<4:0> with extracted clock at RXC. The adaptive equalizer compensates for the distortion of up to 140m of cable and attenuates cable-induced jitter, corrects for DC baseline wander, and converts the MLT-3 signal to 2-level NRZ. The receive PLL extracts clock from the equalized signal, providing additional jitter attenuation, and clocks the signal through the serial to parallel converter. The resulting 5-bit symbols appear at RSM<4:0>. The extracted clock appears at RXC. Resistor RGMSET sets internal time constants controlling the adaptive equalizer's transfer function. RGMSET must be set to 9.53k (1%). LOOPBACK Tying LPBK pin low places the part in loopback mode. Data at TXD<4:0> are serialized, MLT-3 encoded, equalized, then sent to receive PLL for clock recovery and sent to the RXD<4:0> outputs. In this mode, data at TXD<4:0> has to be valid 5-bit symbol data. ML6698 SCHEMATIC Figure 2 shows a general design where the 5-bit and other control signals interface to the controller. TXC is connected to a 25MHz, 100ppm clock oscillator. Inductors L1 and L2 are for the purpose of improving return loss. Capacitor C7 is recommended. It decouples some noise at the inputs of the ML6698 and improves the Bit Error Rate (BER) performance of the board. It is recommended having a 0.1F capacitor on every VCC pin as indicated by C3, 4, 9-12. Also, it is recommended to split the AVCC and DVCC, AGND and DGND. It is recommended that AGND and DGND planes are large enough for low inductance. If splitting the two grounds and keeping the ground planes large enough is not possible due to board space, you could join them into one larger ground plane. DIFFERENCES BETWEEN THE ML6694 AND ML6698 Both parts are pin to pin compatible and perform the same functions. The only differences are: 1. SDO: The ML6694 has SDO (Signal Detect Output) active in 100BASE-TX mode only, while the ML6698 has it active in both 10BASE-T and 100BASE-TX modes. 2. SEL10/100 or SEL100/10: The ML6694 has the 100BASE-TX mode active low and the 10BASE-T mode active high (SEL10/100). The ML6698 has the opposite polarity where the 100BASE-TX mode is active high and the 10BASE-T mode is active low (SEL100/10).
9
ML6698
INPUT FROM A CONTROLLER, OTHERWISE FLOAT
DVCC FB1 + + C4 FB2 OUTPUTS TO A 10BASE-T PHY 1:1 6 5 4 3 2 1 44 43 42 41 40 R23 C1 R10 C7 R11 1 TXTP+ 2 TXTP- 3 RXTP+ 4 5 6 RXTP- 7 8 RJ45 SHIELD GROUNDED C11 C12 C5 AVCC NC 1 4
INPUT FROM A 10BASE-T PHY
U2
2 3
C3
C9
C10
C6
7 PWRDN 8 RSM4 9 RSM3
10BTTXINP
CMREF 39 TPINP 38 TPINN 37
CONTROLLER INTERFACE
10 DGND1 11 RSM2 12 DVCC1 13 RSM1 14 DGND2 15 RSM0 16 RXC
AVCC2 36
10BTTXINN
TSM0
TSM1
TSM2
TSM3
TSM4
AGND1
AVCC1
LPBK
TXC
ML6698 U1
AGND2 35 TPOUTP 34 TPOUTN 33 AGND3 32 RTSET 31 RGMSET 30
R8 AVCC R9
L1
R16 2:1
R15
R18 L2
R17
U5
R21
R19 R22 R20
SEL100/10
17 DGND3
DGND4A
DGND4C
NC 29
DGND4B
DGND5
DVCC2
DVCC5
AVCC3
R2
R1
C8 C2
SDO
NC
26
18 19 DVCC
20
21
22
23
24 25
27
NC
28 AVCC
R1 R2 R8, R9, R23 R10, R11 R15-R20 R21-R22
2.49kW 1%, 1/8W Surface Mount 9.53kW 1%, 1/8W Surface Mount 200W 1%, 1/8W Surface Mount 100W 1%, 1/8W Surface Mount 49.9W 5%, 1/8W Surface Mount 75W 5%, 1/8W Surface Mount
C7 C2 U1 U2 U5
10pF Cap Board Layer Cap (2kV rated) ML6698 44-PLCC Surface Mount Clock Oscillator, 25MHz 4-Pin Surface Mount Bel Transformer Module S558-1287-02, XFMRS Inc. XF6692TX, or Valor ST6129 (not pin compatible) Fair-Rite SM Bead P/N 2775019447 130nH Inductors rated at 50MHz
C1, C3, 0.1F Ceramic Chip Cap C4, C8-C12 C5, C6 10F Tantalum Cap
FB1, FB2 L1, L2
Figure 2. ML6698 Typical Applications Circuit
10
ML6698
PHYSICAL DIMENSIONS
inches (millimeters)
Package: Q44 44-Pin PLCC
0.685 - 0.695 (17.40 - 17.65) 0.650 - 0.656 (16.51 - 16.66) 1 0.042 - 0.056 (1.07 - 1.42) 0.025 - 0.045 (0.63 - 1.14) (RADIUS)
0.042 - 0.048 (1.07 - 1.22) 12
PIN 1 ID 0.650 - 0.656 0.685 - 0.695 (16.51 - 16.66) (17.40 - 17.65) 0.500 BSC (12.70 BSC) 0.590 - 0.630 (14.99 - 16.00)
34
23 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.165 - 0.180 (4.06 - 4.57) 0.148 - 0.156 (3.76 - 3.96) 0.009 - 0.011 (0.23 - 0.28) 0.100 - 0.112 (2.54 - 2.84)
0.013 - 0.021 (0.33 - 0.53)
SEATING PLANE
Package: H44-10 44-Pin (10 x 10 x 1mm) TQFP
0.472 BSC (12.00 BSC) 0.394 BSC (10.00 BSC) 34 1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC) 0 - 8 0.003 - 0.008 (0.09 - 0.20)
23 12 0.032 BSC (0.80 BSC) 0.012 - 0.018 (0.29 - 0.45) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05)
0.018 - 0.030 (0.45 - 0.75)
SEATING PLANE
11
ML6698
ORDERING INFORMATION
PART NUMBER ML6698CQ (End Of Life) ML6698CH TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 44-PIN PLCC (Q44) 44-PIN TQFP (H44-10)
(c) Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295
Ds6698-01
12

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